SAI VIDYA INSTITUTE OF TECHNOLOGY
Department of Electronics and Communication Engineering
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Module-5 Notes is Now Available in Website

Sunday, November 26, 2017

VERILOG HDL(15EC53) MODULE 5 NOTES

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VERILOG HDL(15EC53) MODULE 5 

 Introduction to VHDL
Introduction: Why use VHDL?, Shortcomings, Using VHDL for Design Synthesis, Design tool flow, Font conventions.
Entities and Architectures: Introduction, A simple design, Design entities, Identifiers, Data objects, Data types, and Attributes.


Sunday, November 12, 2017

VERILOG HDL (15EC53) EXERCISE EXAMPLES AND SOLUTIONS

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VERILOG HDL (15EC53) EXERCISE EXAMPLES AND SOLUTIONS



VERILOG HDL(15EC53) MODULE 4 NOTES

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VERILOG HDL(15EC53) MODULE 4 NOTES

SYLLABUS:   Behavioral Modeling Structured procedures, initial and always, blocking and non-blocking statements, delay control, generate statement, event control, conditional statements, Multiway branching, loops, sequential and parallel blocks.

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