SAI VIDYA INSTITUTE OF TECHNOLOGY
Department of Electronics and Communication Engineering
***Verilog-HDL***Verilog-HDL***Verilog-HDL***Verilog-HDL***Verilog-HDL***Verilog-HDL***Verilog-HDL***Verilog-HDL***Verilog-HDL***Verilog-HDL***Verilog-HDL***
Module-5 Notes is Now Available in Website

Friday, December 1, 2017

VERILOG HDL(15EC53) QUESTION BANK (Module 1 to Module 5)

2 comments :
VERILOG HDL(15EC53) QUESTION BANK (Module 1 to Module 5) including model paper and Exercise examples 


Sunday, November 26, 2017

VERILOG HDL(15EC53) MODULE 5 NOTES

No comments :
VERILOG HDL(15EC53) MODULE 5 

Introduction to VHDL
Introduction: Why use VHDL?, Shortcomings, Using VHDL for Design Synthesis, Design tool flow, Font conventions.
Entities and Architectures: Introduction, A simple design, Design entities, Identifiers, Data objects, Data types, and Attributes.


Sunday, November 12, 2017

VERILOG HDL (15EC53) EXERCISE EXAMPLES AND SOLUTIONS

No comments :
VERILOG HDL (15EC53) EXERCISE EXAMPLES AND SOLUTIONS



VERILOG HDL(15EC53) MODULE 4 NOTES

No comments :
VERILOG HDL(15EC53) MODULE 4 NOTES

SYLLABUS:   Behavioral Modeling Structured procedures, initial and always, blocking and non-blocking statements, delay control, generate statement, event control, conditional statements, Multiway branching, loops, sequential and parallel blocks.

Sunday, October 15, 2017

Verilog HDL Assignment 2

No comments :
Verilog HDL Assignment 2


VERILOG HDL(15EC53) MODULE 3 NOTES

No comments :
Verilog HDL Module 3 .
Gate-Level Modeling
Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall and turn-off delays, min, max, and typical delays.
Dataflow Modeling
Continuous assignments, delay specification, expressions, operators, operands, operator types.

Tuesday, September 12, 2017

MODULE 2 QUESTION BANK (15EC53)

No comments :
Module 2 Question Bank (15EC53)


MODULE 1 QUESTION BANK (15EC53)

No comments :
Module 1 Question Bank (15EC53)


VERILOG HDL(15EC53) MODULE 2 NOTES

No comments :
VERILOG HDL(15EC53) MODULE 2  NOTES

Syllabus: Basic Concepts Lexical conventions, data types, system tasks, compiler directives.
Modules and Ports, Module definition, port declaration, connecting ports, hierarchical name referencing.

Monday, September 11, 2017

VERILOG HDL- MODEL QUESTION PAPER (15EC53)

No comments :
Verilog HDL MODEL Question Paper (15ec53)


ASSIGNMENT 1

1 comment :
ASSIGNMENT 1                                             DUE DATE FOR SUBMISSION:15/09/2017

Tuesday, August 29, 2017

VERILOG HDL(15EC53) MODULE 1 NOTES

No comments :
Verilog HDL Module 1 Notes

Syllabus: Overview of Digital Design with Verilog HDL Evolution of CAD, emergence of HDLs, typical HDL-flow, why Verilog HDL?, trends in HDLs. Hierarchical Modelling Concepts Top-down and bottom-up design methodology, differences between modules and module instances, parts of a simulation, design block, stimulus block.


/view?usp=sharing

VERILOG HDL 15EC53 SYLLABUS (CBCS SCHEME)

No comments :
Verilog HDL_15EC53_ Syllabus (CBCS)
F